1. Field of the Invention
The present invention relates to a data processing system and an access control method in a flash memory used in the data processing system.
2. Description of the Related Art
A flash memory is a kind of EEPROM, and data can be newly written by erasing data in units of blocks. Even if power is not supplied to the flash memory, data stored in the flash memory is not lost. For this reason, the flash memory is used for memory cards such as a digital camera and a home game machine, and the storage of BIOS of a personal computer or the like.
With reference to FIGS. A-1 to 1K-2 and FIG. 2, an operation when a data rewriting process through additional data write process by using a plurality of blocks, e.g., two blocks will be briefly described in a conventional flash memory.
FIGS. 1A-1 to 1K-2 are diagrams showing the states when the data rewriting process is carried out by using two blocks 0 and 1 with three data areas 0 to 2 in the conventional flash memory. The data reading process shown in FIG. 2 is carried out under the control of a user application software.
When the data is additionally written in the flash memory, the same data is written in each of the blocks 0 and 1. Herein, the data areas are in the initial state in which an initial value “FFH” is stored in each data area, and the additional write of the data “d1” to “d3” and a data erasing process of the blocks are sequentially carried out. It should be noted that when both the read out data from both the blocks 0 and 1 are the initial value “FFH”, or when both the read out data are not coincident with each other, a predetermined default value “d0” is used.
For example, when the data “d1” is written, after the data “d1” is written in the data area 0 of the block 0 as shown in FIG. 1B-1, the data “d1” is written in the data area 0 of the block 1 as shown in FIG. 1C-2. In the state shown in the FIGS. 1C-1 and 1C-2, the data “d1” is read as valid data. The areas of the blocks where data are written are shown by meshes in FIGS. 1A-1 to 1K-2.
When the data rewriting process through the data additional write is carried out by using two blocks (0) and (1) of the conventional flash memory, and the block (0) is full, the same data as that of the block (0) is written in the block (1). Then, the data of the block (0) is erased for writing new data, as shown in FIG. 1H-1 if the block (1) is full.
In the data reading process from the conventional flash memory, as shown in FIG. 2, a read voltage level is firstly set in the conventional flash memory (step 1101). The read voltage level is needed to read out the data from the conventional flash memory by a CPU. Then, the latest data are read out from each of the block 0 and block 1 by using the set read voltage level (steps 1102 and 1103). For example, as shown in FIGS. 1C-1 and 1C-2, the data “d1” stored in the data area 0 of the block 0 and the data “d1” stored in the data area 0 of the block 1 are read out as the latest data.
Subsequently, the data read out from the two blocks are compared (step 1104). When the two data coincide with each other, the read out data are determined to be valid (step 1105). When the two data do not coincide with each other, a predetermined default data “d0” is set as data of the flash memory (step 1106). For example, when the data are read at the timing shown in FIGS. 1C-1 and 1C-2, the data “d1” is determined to be valid since the data “d1” read out from the block 0 and the block 1 coincide with each other.
The default data “d0” is set as valid data at the timing shown in FIG. 1B-1 and 1B-2, since the data read out from the block 0 is the data “d1” and the data read out from the block 1 is the data “FFH”, and the data read out from the block 0 and the data read out from the block 1 do not coincide with each other in the comparison of the step 1104. Since the data read out from the block 0 is the data “d2” and the data read out from the block 1 is the data “d1” in FIGS. 1D-1 and 1D-2, the data read out from the block 0 and the data read out from the block 1 do not coincide with each other, and the default data “d0” becomes the valid data. A method of using the last coincidence data instead of the default data may be adopted in case of data incoincidence.
FIGS. 1A-1 to 1K-2 and FIG. 2 show a case where the coincidence determination of the read data is carried out by using the two blocks. Also, a method for determining the valid data by the majority decision of the latest data read out from three blocks is known in a data rewriting process using three blocks. For example, the method of determining the valid data by the majority decision is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-325953).
However, various problems described below exist in the above-described data access control method in the conventional flash memory.
When the data rewriting process is interrupted at timing t during the additional data write into the data area 0 of the block 1 due to a cause such as a power fault in the conventional flash memory, as shown in FIGS. 1B-1 and 1B-2, there would be a possibility that the coincidence of the data between the two blocks is diminished, so that the latest data cannot be used.
The reason is that it is impossible to determine whether the data of either block is valid. Therefore, the default data is used as a valid data. When the process is interrupted due to the power fault at the timing shown by “t” in FIGS. 1A-1 to 1K-2, it is determined that data are not coincident with each other and the latest data is not held, even if the latest data is actually stored in the block. Since it is necessary to erase the data when the data areas of the block have been fully used through the data rewrite, the valid data cannot be determined in a state where one of the blocks is erased, in the same manner as the above procedure.
When the valid data is determined based on the majority decision by using three or more blocks as disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-325953), the validity of the data of each block cannot be guaranteed when the data rewriting process is interrupted due to the cause such as the power fault. Therefore, there would be a possibility that the valid data cannot be accurately determined. Also, when a method for determining the valid data is carried out based on the majority decision by using three or more blocks, the data area has large waste since the same data is written in multiple blocks.